Methods and systems for multimedia data processing

ABSTRACT

In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes defining one or more pixel block regions in a first cache so as to cache a plurality of reference pixel blocks corresponding to reference data. A reference pixel block from among the plurality of reference pixel blocks is assigned to a pixel block region from among the one or more pixel block regions based on a predetermined criterion. The reference pixel block is associated with a tag based on the pixel block region so as to facilitate a search of the reference data in order to process a plurality of pixel blocks associated with a multimedia frame of the multimedia data.

TECHNICAL FIELD

The present disclosure generally relates to the field of dataprocessing.

BACKGROUND

In an exemplary scenario, a rapid advancement in techniques related tomultimedia data processing may place increased demands on the respectivecomputing powers of various multimedia processors. The multimedia dataprocessing may involve the encoding of multimedia data for compressionpurposes. The compression of multimedia data may be performed in orderto save memory during storage or to efficiently utilize the availablebandwidth during a transmission. The multimedia data may be encodedutilizing encoding mechanisms that are sufficient to achieve acompression of the multimedia data. The multimedia data may subsequentlybe decompressed (for example, decoded) for display/viewing purposes.

Moreover, in an exemplary scenario, various video coding paradigms mayinvolve the encoding of frames corresponding to the multimedia databased on reference frames, thereby optimizing storage capacity and alsoenhancing a performance of the multimedia processors. In an exemplaryscenario, the multimedia data processing may involve performing motioncompensation, wherein reference pixels associated with a reference frame(for example, a previously decoded frame and stored in a memory) arefetched from a memory and interpolated to form a prediction frame. Theprediction frame may be subtracted from a current frame to obtainresidual samples corresponding to the current frame. The residualsamples may then be encoded for the encoding of the current frame. In anexemplary scenario, while performing motion compensation, the referencepixels are fetched (for encoding various portions of the frame) randomlyfrom the memory and a significant degree of overlap may exist among thefetched reference pixels. Pursuant to an exemplary scenario, a memorybandwidth consumption and a power dissipation may increase as a resultof the random nature of fetching reference pixels.

SUMMARY

Methods and systems for multimedia data processing are disclosed. In oneembodiment, in order to process a multimedia frame, the multimedia frameis divided into a plurality of block partitions, with each partitionincluding a plurality of pixel blocks. In one embodiment, a firstreference region is determined for the plurality of pixel blocksassociated with the first block partition of the multimedia frame. Inone embodiment, prior to fetching the first reference region from thememory, a presence of the first reference region is determined in afirst cache. If the first reference region is determined to beunavailable in the first cache, then a presence of the first referenceregion is checked in the second cache. If the first reference region isdetermined to be unavailable in the second cache, the first referenceregion is fetched from the memory.

In one embodiment, the method includes defining one or more pixel blockregions in the first cache so as to cache a plurality of reference pixelblocks corresponding to reference data. A reference pixel block fromamong the plurality of reference pixel blocks is assigned to a pixelblock region from among the one or more pixel block regions based on apredetermined criterion. The reference pixel block is associated with atag based on the pixel block region so as to facilitate a search of thereference data in order to process a plurality of pixel blocksassociated with a multimedia frame of the multimedia data.

In an embodiment, the search of the reference data includes identifyingpixel block regions from among the one or more pixel block regions thatare likely to include the first reference region by comparing taginformation associated with the first reference region with spaninformation associated with one or more pixel block regions. Further, apresence of one or more reference pixel blocks associated with the firstreference region is determined in the identified one or more pixel blockregions. In an embodiment, determining the presence of the one or morereference pixel blocks includes determining a possible offset of thefirst reference region within each of the identified one or more pixelblock regions based on the span information and a location of the firstreference region within a reference frame associated with the referencedata. A presence of the first reference region at the determinedpossible offset in the identified one or more pixel block regions may bedetermined by checking a plurality of availability tags associated witheach reference pixel block at the determined possible offset.

In an embodiment, a minimum granularity for fetching a reference pixelblock from among the one or more reference pixel blocks associated withthe first reference region from the memory is matched with a minimumgranularity of caching in a pre-fetch buffer associated with the memory.In an embodiment, one or more additional reference pixel blocks adjacentto the one or more reference pixel blocks associated with the firstreference region within the reference frame and forming a rectangularregion within the reference frame are fetched together. In anembodiment, the one or more additional reference pixel blocks and thefirst reference region correspond to a block partition from among aplurality of block partitions within the reference frame. In anembodiment, the one or more additional reference pixel blocks and thefirst reference region correspond to adjacent block partitions withinthe reference frame.

In one embodiment, a system configured to process multimedia data isdisclosed. The system includes a memory, a cache unit and a processingunit. The memory is configured to store one or more reference framescorresponding to reference data. The cache unit is communicativelyassociated with the memory and comprises a first cache and a secondcache. The processing unit is communicatively associated with the memoryand the cache unit and is configured to define one or more pixel blockregions in the first cache so as to cache a plurality of reference pixelblocks corresponding to the reference data. The processing unit isfurther configured to (1) assign the reference pixel block from amongthe plurality of reference pixel blocks to a pixel block region fromamong the one or more pixel block regions based on a predeterminedcriterion and (2) associate the reference pixel block with a tag basedon the pixel block region so as to facilitate a search of the referencedata in order to process a plurality of pixel blocks associated with amultimedia frame.

In one embodiment, a computer-readable medium storing a set ofinstructions that when executed cause a computer to perform a method formultimedia data processing is disclosed. The method includes definingone or more pixel block regions in a first cache so as to cache aplurality of reference pixel blocks corresponding to reference data. Thereference data may be associated with a reference frame. The method alsoincludes assigning a reference pixel block from among the plurality ofreference pixel blocks to a pixel block region from among the one ormore pixel block regions based on a predetermined criterion.Additionally, the method includes associating the reference pixel blockwith a tag based on the pixel block region so as to facilitate a searchof the reference data in order to process a plurality of pixel blocksassociated with a multimedia frame.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of an exemplary system configured to processmultimedia data according to an embodiment;

FIG. 2 illustrates a plurality of exemplary pixel block regions definedin a first cache according to an embodiment;

FIGS. 3A-3C illustrate an exemplary exploitation of the overlap betweena plurality of reference data fetches, such as by using the system ofFIG. 1, according to an embodiment;

FIG. 4A depicts a simplified overview of an exemplary process flowillustrating a processing of a multimedia frame associated withmultimedia data according to an embodiment;

FIG. 4B illustrates an exemplary scheduling of read/write operationsassociated with the first cache during a processing of the multimediaframe according to an embodiment;

FIG. 5 illustrates an exemplary process of a search of reference data inorder to process a plurality of pixel blocks associated with amultimedia frame according to an embodiment;

FIGS. 6A-6C illustrate exemplary fetching reference pixel blocksadjacent to one another within a reference frame associated withreference data according to an embodiment;

FIG. 7 is a flow chart illustrating an exemplary method of multimediadata processing according to an embodiment; and

FIGS. 8A-8B collectively show a flow chart illustrating an exemplarymethod of a reference data search in order to perform a processing ofthe multimedia frame according to an embodiment.

DETAILED DESCRIPTION

In an exemplary scenario, multimedia data processing may involveperforming motion compensation for frames corresponding to multimediadata. In an exemplary scenario, while performing motion compensation,reference pixels are fetched (for encoding various portions of theframe) randomly from the memory, and a significant degree of overlapexists among the fetched reference pixels. Pursuant to an exemplaryscenario, a memory bandwidth consumption and a power dissipation mayincrease as a result of the random nature of fetching reference pixels.

Various embodiments of the present technology provide certain advantagesand benefits in the field of multimedia data processing. The followingdescription and accompanying figures demonstrate that the presenttechnology may be practiced or otherwise implemented in a variety ofdifferent embodiments. It is noted, however, that the present technologyis not limited to any or all of the specifically disclosed embodiments.Indeed, one or more of the devices, features, operations, processes, orother qualities of a specifically disclosed embodiment may be removed,replaced, added to, or changed.

FIG. 1 is a block diagram of an exemplary system 100 configured toprocess multimedia data according to an embodiment. In an embodiment,the system 100 is configured to be a video codec (for example, videoencoder/decoder) for processing of the multimedia data. In anembodiment, the system 100 is configured to be included within amultimedia system. In an embodiment, the system 100 is configured to beexternal to the multimedia system and is communicatively associated withthe multimedia system. Examples of the multimedia system may include,but are not limited to: (1) multimedia devices, such as, for example,cellular phones, digital video cameras and digital camcorders; (2) dataprocessing devices, such as, for example, personal computers, laptopsand personal digital assistants; and (3) consumer electronics, such as,for example, set top boxes, digital video disk (DVD) players and videonetwork servers. Pursuant to an exemplary scenario, the system 100 maybe any machine capable of executing a set of instructions (sequentialand/or otherwise) so as to perform processing of the multimedia data.

The multimedia data may be received by the system 100 from a mediacapture device. Examples of the media capture device may include a videocamera or a camcorder. The media capture device may be, for example, astand-alone device or a part of a mobile device, such as, for example, aSmartphone, or a data processing device, such as, for example, apersonal computer, a laptop device or a personal digital assistant(PDA). The multimedia data may also be received by the system 100 from atranscoding system (which may be implemented, for example, in any ofhardware, software and/or firmware), which may be a stand-alone deviceor a part of the media capture device.

Pursuant to an exemplary scenario, the multimedia data may include asequence of multimedia frames (hereinafter interchangeably referred toas “frames”), and each frame from among the sequence of frames mayinclude a plurality of blocks (for example, macro blocks) of multimediadata. Examples of multimedia data may include, but are not limited to,audio data, video data, audio-video (A/V) data, image data, textual dataand combinations thereof. An example of processing of the multimediadata may include performing motion compensation for the framescorresponding to the multimedia data for encoding/decoding purposes.Performing motion compensation for a frame of multimedia data involvesencoding/decoding the frame with respect to a reference frame (forexample, a previously decoded frame). In an embodiment, one or morereference pixels associated with the reference frame may be interpolatedto configure a prediction frame in order to encode the frame. Theprediction frame may be subtracted from the frame to obtain residualsamples corresponding to the frame. The residual samples may then beencoded in order to encode the frame.

The system 100 includes a processing unit 102, a memory 104, a cacheunit 106 and a bus 108. In an embodiment, the processing unit 102 may beembodied as a multi-core processor, a single core processor, or acombination of one or more multi-core processors and one or more singlecore processors. For example, the processing unit 102 may be embodied asone or more of various processing devices, such as a coprocessor, amicroprocessor, a controller, a digital signal processor (DSP),processing circuitry with or without an accompanying DSP, or variousother processing devices including integrated circuits such as, forexample, an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), a microcontroller unit (MCU), a hardwareaccelerator, a special-purpose computer chip, or the like. In anembodiment, the processing unit 102 may be configured to executehard-coded functionality. In an embodiment, the processing unit 102 isembodied as an executor of software instructions, wherein theinstructions may specifically configure the processing unit 102 toperform the algorithms and/or operations described herein when theinstructions are executed. The processing unit 102 may include, amongother things, a clock, an arithmetic logic unit (ALU) and logic gatesconfigured to support an operation of the processing unit 102. In anembodiment, the memory 104 is configured to store the multimedia data.In an embodiment, the memory 104 is configured to store reference data(for example, in the form of a plurality of reference frames) in orderto process multimedia frames associated with the multimedia data.

In an embodiment, decoded frames of multimedia data may be stored in thememory 104 as the reference frames corresponding to the reference data.Examples of the memory 104 include, but are not limited to, a randomaccess memory (RAM), a dual port RAM, a synchronous dynamic RAM (SDRAM),a double data rate SDRAM (DDR SDRAM), and the like. In an embodiment,the cache unit 106 is configured to cache frequently used reference datastored in the memory 104. As a result of limited bandwidth and hightraffic conditions associated with the memory 104, storing the referencedata in the cache unit 106 increases a processing performance associatedwith the system 100. The cache unit 106 includes a first cache 106 a anda second cache 106 b. In an embodiment, the first cache 106 a mayinclude one or more cache banks that may be implemented to cache thereference data. More specifically, a storage space associated with thefirst cache 106 a may be considered to be partitioned (for example, intophysical partitions or virtual partitions) and each such partition maybe referred to as a cache bank, which may be utilized to cache thereference data. The cache banks are explained further herein withreference to FIG. 4B. In an embodiment, the second cache 106 b mayinclude one or more cache banks that may be implemented to cache thereference data. In an embodiment, the processing unit 102, the memory104 and the cache unit 106 are configured to be communicativelyassociated, coupled or connected with each other via or through the bus108. Examples of the bus 108 may include, but are not limited to, a databus, an address bus, a control bus, and the like.

The bus 108 may be, for example, a serial bus, a bi-directional bus or aunidirectional bus. For multimedia data processing, each framecorresponding to the multimedia data may be divided into a plurality ofpixel blocks. For example, the frame may be divided into a plurality of16×16 pixel blocks, which may be referred to, for example, as amacroblock. Each such macroblock may further be partitioned into parts,such as, for example, into four partitions, wherein each partition maycomprise four 4×4 pixel blocks. Each such partition of pixel blocks maybe referred to herein as a block partition. As explained above, in orderto process the frame, reference data may be fetched for various portionsof the frame, such as for a plurality of pixel blocks associated with ablock partition of the frame. In an embodiment, the processing unit 102is configured to determine the reference data that is to be implementedto process the plurality of pixel blocks associated with the blockpartition of the frame of the multimedia data.

As explained, the reference data is stored in the memory 104 in the formof one or more reference frames. Each of the one or more referenceframes includes one or more reference pixel blocks. It is noted that theterminology ‘reference pixel block’ may be construed as referring to,for example, an ‘m×n’ block of pixels within the reference frameassociated with the frame of multimedia data, where m and n are positiveintegers. Determining the reference data that is to be implemented toprocess the plurality of pixel blocks associated with each blockpartition of the frame of the multimedia data may include determiningthe reference pixel blocks in the reference frames that may be utilizedfor processing purposes. In an embodiment, the reference pixel blocksfetched from the memory 104 are stored in the cache unit 106 for ease offuture access of the reference data.

In an embodiment, the processing unit 102 is configured to define one ormore pixel block regions in the first cache 106 a associated with thecache unit 106 so as to cache the plurality of reference pixel blockscorresponding to reference data previously fetched from the memory 104.A pixel block region may be considered as an allotment of storage spacewithin the first cache 106 a, which is capable of caching one or morereference pixel blocks. One or more such storage spaces may be definedwithin the first cache 106 a in order to cache the plurality ofreference pixel blocks fetched from the memory 104. In an embodiment, apixel block region may be associated with a cache bank from among theone or more cache banks of the first cache 106 a. In an embodiment, thenumber of pixel block regions to be defined may be determined based on avideo compression paradigm. Examples of the video compression paradigmsinclude, but are not limited to video coding experts group (VCEG),H.120, H.261, moving pictures experts group (MPEG), MPEG-1 Part 2, H.262or MPEG-2 Part 2, H.263, MPEG-4 Part 2, H.264 or MPEG-4 AVC, VC-2(Dirac), high efficiency video coding (HEVC) and the like.

In an embodiment, each pixel block region is defined through spaninformation, a base address, a cache bank identification tag, and/or areference index. The span information is indicative of dimensions alonga length direction (e.g., a height) and a width direction (e.g., awidth) of each pixel block region. The base address is offset from, orwith respect to, a top left address (for example, pixel co-ordinates ofthe top left pixel location) of each pixel block region from an originpre-determined within a space defined by the reference frame and isindicative of the locality of the pixel block region within the spacedefined by the reference frame. The base address of each pixel blockregion is expressed in terms of x and y coordinates. The cache bankidentification tag is indicative of a cache bank with which each pixelblock region is associated. The reference index is indicative of thereference frame associated with each pixel block region. For example, ifthe reference data in the memory 104 includes 32 reference frames andthe pixel block region is associated with reference frame #5 of the 32reference frames, then the reference index of the pixel block region mayindicate the reference frame #5 from which the reference pixel blocksincluded in the pixel block region are fetched.

In an embodiment, the processing unit 102 is also configured to assignthe reference pixel block from among the plurality of reference pixelblocks corresponding to the reference data to a pixel block region fromamong the one or more pixel block regions. In an embodiment, theprocessing unit 102 assigns the reference pixel block to the pixel blockregion based on a predetermined criterion. In an embodiment, thepredetermined criterion includes, but is not limited to, a locality ofthe reference pixel block within the space defined by the referenceframe.

In an embodiment, each reference pixel block is associated with a tagbased on the pixel block region so as to facilitate a search of thereference data in order to process a plurality of pixel blocksassociated with the frame of the multimedia data. In an embodiment, thetag may be configured to provide an indication of a location of thereference pixel block within the pixel block region. In an embodiment,the tag may be defined based on an offset of the reference pixel blockfrom a base address associated with the corresponding pixel blockregion. In an example embodiment, the width and height of each of thepixel block regions is 32 pixels×32 pixels, and a granularity of thepixel block region is 4×4 pixel blocks. Accordingly, eight 4×4 referencepixel blocks may be included along each of the x and y directions. Each4×4 reference pixel block may be associated with a tag based on anoffset from the base address of the corresponding pixel block region.The offset along the x and y directions would each utilize 3 bits, andtherefore the size of each tag is 6 bits. The 4×4 pixel blocks may besearched in each of the one or more pixel block regions based on thetag.

In various exemplary caching techniques, the reference data in thememory is organized in the form of 4×4 reference pixel blocks, and eachof the 4×4 reference pixel blocks in the memory is associated with a tagindicating a displacement along an x direction and a displacement alonga y direction in a space defined by the reference frame. Consideringthat a maximum size of the reference frame is 8K×8K pixels in accordancewith one or more multimedia coding paradigms, the number of 4×4reference pixel blocks along the x and y directions would be 2K each.Since the 4×4 pixel blocks are tagged based on the x and y coordinates,a size of the tag would be 11 bits for x and 11 bits for y, totaling upto 22 bits. Also, each 4×4 pixel block fetched from memory is taggedwith respect to the reference frame to which the 4×4 pixel blockbelongs. Some of the multimedia coding paradigms, such as, for example,H.264, allow up to 32 reference frames in the memory. Tagging based on32 reference frames leads to an addition of 5 bits to the tag.Therefore, a size of the tag for each reference pixel block may be 27bits when 32 reference frames are utilized. In an embodiment, about 288tags are utilized to perform a good caching. Since the size of each tagis 27 bits, 288 27-bit comparisons are involved during the caching.Performing 288 27-bit comparisons in order to determine and fetchreference data would dissipate a significant amount of power. Definingpixel block regions in the first cache 106 a and tagging reference pixelblocks as offset from the base address of the corresponding pixel blockregion reduces a size of the tag from 27 bits to 6 bits, therebyreducing a cost of comparison and leading to a sizable savings in powerconsumption.

In an embodiment, a minimum granularity for fetching each of the one ormore reference pixel blocks from the memory 104 is matched with aminimum granularity to cache in a pre-fetch buffer associated with thememory 104 for optimal performance of the memory 104. For example, ifthe data organization in the pre-fetch buffer is block-based, then thefetching of the reference pixel blocks is aligned to be in blocks,thereby optimizing a fetching of the reference data. Similarly, if thedata organization in the pre-fetch buffer is line-based (for example,rows of reference data fetches are sequentially fetched), then thefetches of reference pixels are aligned to be line-based reference datafetches. In an embodiment, each pixel block region is sparsely filledand includes a select few reference pixel block entries (also referredto as elements). In an embodiment, each of the one or more pixel blockregions includes nine elements i.e., nine reference pixel blocks areassociated with each pixel block region. In an embodiment, each elementassociated with a pixel block region is assigned a specific locationwithin the pixel block region based on its location within acorresponding reference frame.

In an embodiment, reference pixel blocks belonging to a single referenceframe are assigned to a pixel block region from among the one or morepixel block regions. In an embodiment, each pixel block region isdefined within a cache bank from among the one or more cache banksassociated with the first cache 106 a. In an embodiment, a cache bankidentification tag is associated with each pixel block region so as toindicate the cache bank within which each pixel block region is defined.

In an embodiment, the second cache 106 b is organized so as to cache thereference data associated with a first block partition from among aplurality of block partitions associated with the multimedia data inorder to render the reference data available during the processing ofone or more subsequent block partitions of the multimedia data. In anembodiment, the pixel blocks within a frame of multimedia data areprocessed in a raster scan order. It is noted that the terminology“raster scan order” may be construed as referring to, for example, aleft to right and a top to bottom order. Accordingly, pixel blocks in arow are processed from left to right followed by the pixel blocks insubsequent rows within the frame of multimedia data. During theprocessing of one or more subsequent rows associated with the frame, thereference data associated with one or more previous rows may havealready been deleted from the first cache 106 a. However, the pixelblocks in adjacent rows of the frame may have a commonality in thereference data fetches. The second cache 106 b disclosed herein enablesthe exploitation of the commonality in reference data fetches foradjacent rows of the frame. In an embodiment, the second cache 106 b isdefined to have a span along a width direction equivalent to a width ofa block partition of the frame and a variable dimension along a lengthdirection (e.g. a height), depending on a configuration of the system100.

In an embodiment, the reference data fetched from the memory 104 ispopulated in the second cache 106 b if the reference pixel blocksassociated with the reference data lie within the span of the secondcache 106 b. In an embodiment, reference data cached in the first cache106 a is populated in the second cache 106 b upon an expiration of thereference data in the first cache 106 a. In an embodiment, the referencedata cached in the first cache 106 a expires one cache bank at a timeupon all (or a preselected amount) of the reference data stored in thecache bank being read from the cache bank. During the processing of thesubsequent rows of the frame, an availability of space within the secondcache 106 b is determined in order to cache the fetched reference pixelblocks. If the space in the second cache 106 b is determined to beavailable, the fetched reference pixel blocks are populated in thesecond cache 106 b. In an embodiment, one or more previously cachedreference pixel blocks in the second cache 106 b are deleted if thespace in the second cache 106 b is determined to be unavailable. Anorigin of the second cache 106 b is shifted by a predetermined margin inorder to cache the fetched reference pixel blocks upon deleting the oneor more previously cached reference pixel blocks. The origin is shiftedto facilitate the simultaneous reading of reference data from a row ofthe second cache 106 b while writing reference data into another row ofthe second cache 106 b. In an embodiment, the second cache 106 b isorganized in a block-based manner, and the reference data populated inthe second cache 106 b is tagged with a displacement in horizontaland/or vertical directions.

In one embodiment, the second cache 106 b is organized in a line-basedmanner. Additionally, in an embodiment, if the reference data isdetermined to be absent in the first cache 106 a, the reference data issearched in the second cache 106 b. If the reference data is determinedto be present in the second cache 106 b, the reference data is assignedto one of the pixel block regions of the first cache 106 a for futurereference pixel fetches. Pursuant to one embodiment, however, if thereference data is determined to be unavailable, i.e. absent in thesecond cache 106 b, the reference data is fetched from the memory 104. Anumber of processing cycles (for example, 10 processing cycles) utilizedfor fetching the reference data from the second cache 106 b is lesserthan the number of processing cycles (for example, 100 processingcycles) utilized for fetching the reference data from the memory 104. Inan embodiment, the second cache 106 b is “one way associative/directmapped” such that each entry in the memory 104 is cached at oneparticular location in the second cache 106 b. In an embodiment, aplurality of luminance (hereinafter referred to as “luma”) componentsand a plurality of chrominance (hereinafter referred to as “chroma”)components of the reference data are cached separately in the secondcache 106 b and/or the memory 104. In an embodiment, the luma componentsare organized in the memory 104 and/or the second cache 106 b as 4×4pixel blocks, and the chroma components are organized as 8×2 pixelblocks.

In an embodiment, the processing unit 102 is configured to fetch one ormore additional reference pixel blocks adjacent to the one or morereference pixel blocks associated with the first reference region withinthe reference frame and forming a rectangular region within thereference frame. In an embodiment, the one or more additional referencepixel blocks and the first reference region correspond to a blockpartition from among a plurality of block partitions within thereference frame. In an embodiment, the one or more additional referencepixel blocks and the first reference region correspond to adjacent blockpartitions within the reference frame. In an embodiment, processing unit102 is configured to generate a memory fetch command in order to fetchthe one or more additional reference pixel blocks and the one or morereference pixel blocks associated with the first reference region fromthe memory 104. In an embodiment, processing unit 102 is furtherconfigured to fetch the one or more additional reference pixel blocksand the one or more reference pixel blocks associated with the firstreference region from the memory based on the generated memory fetchcommand.

In an embodiment, the system 100 additionally includes components, suchas an input unit (e.g., an image processing device), a video displayunit (e.g., liquid crystals display (LCD), a cathode ray tube (CRT), andthe like), a cursor control device (e.g., a mouse), a drive unit (e.g.,a disk drive), a signal generation unit (e.g., a speaker) and/or anetwork interface unit. The input unit is configured to transfer themultimedia data to the processing unit 102 for processing of themultimedia data. The drive unit includes a machine-readable medium uponwhich is stored one or more sets of instructions (e.g., software)embodying one or more of the methodologies and/or functions describedherein. In an embodiment, the software resides, either completely orpartially, within the memory 104 and/or within the processing unit 102during the execution thereof by the system 100, such that the memory 104and processing unit 102 also constitute a machine-readable media. Thesoftware may further be transmitted and/or received over a network viathe network interface unit.

The term “machine-readable medium” may be construed to include a singlemedium and/or multiple media (e.g., a centralized and/or distributeddatabase, and/or associated caches and servers) that store the one ormore sets of instructions. Moreover, the term “machine-readable medium”may be construed to include any medium that is capable of storing,encoding and/or carrying a set of instructions for execution by thesystem 100 and that cause the system 100 to perform any one or more ofthe methodologies of the various embodiments. Furthermore, the term“machine-readable medium” may be construed to include, but shall not belimited to, solid-state memories, optical and magnetic media, andcarrier wave signals.

FIG. 2 illustrates a plurality of exemplary pixel block regions definedin a first cache 106 a according to an embodiment. In FIG. 2, threepixel block regions, such as a first pixel block region 202 a, a secondpixel block region 202 b, and a third pixel block region 202 c aredepicted. It is noted that a plurality of such pixel block regions maybe defined in the first cache 106 a in order to cache the referencepixel blocks fetched from one of the second cache 106 b and the memory104. As explained herein with reference to FIG. 1, each pixel blockregion may be considered as an allotment of storage space within thefirst cache 106 a that is capable of caching a plurality of referencepixel blocks. In an embodiment, a number of pixel block regions definedis determined based on a video compression paradigm.

Further, as explained herein with reference to FIG. 1, each pixel blockregion is defined through the span information, the base address, and/orthe reference index. In an embodiment, the base address for a pixelblock region may be defined in terms of displacement of a pixel blockregion from a pre-defined location (referred to herein as the “origin”)within a storage space defined by the first cache 106 a. In anembodiment, the origin may be associated with co-ordinates (0, 0) andthe displacement of a left topmost pixel corresponding to a pixel blockregion from the origin be measured to compute the displacement in x andy directions for defining the base address corresponding to the pixelblock region. In FIG. 2, the first pixel block region 202 a is depictedto be associated with a displacement of BA0_X along the x-direction anda displacement of BA0_Y along the y-direction from the origin (0, 0) andis defined by a base address (BA0_X, BA0_Y). The second pixel blockregion 202 b is depicted to be associated with a displacement of BA1_Xalong the x-direction and a displacement of BA1_Y along the y-directionfrom the origin (0, 0) and is defined by a base address of (BA1_X,BA1_Y). Similarly, the third pixel block region 202 c is depicted to beassociated with a displacement of BA2_X along the x-direction and adisplacement of BA2_Y along the y-direction from the origin (0, 0) andis defined by a base address of (BA2_X, BA2_Y).

Each reference pixel block corresponding to the reference data fetchedfor processing the plurality of pixel blocks of the frame is assigned toa pixel block region from among the one or more pixel block regions. Inan embodiment, each of the one or more reference pixel blocks is a 4×4block of pixels. In an embodiment, each reference pixel blockcorresponding to the reference data is assigned to the pixel blockregion based on a predetermined criterion. In an embodiment, thepredetermined criterion includes, but is not limited to, a locality ofthe reference pixel block within the space defined by the referenceframe (for example, the reference frame in the memory 104 from which thereference pixel block has been fetched). Each of the plurality of pixelblock regions may include one or more reference pixel blocks assignedtherein.

In order to process a pixel block of the frame, the reference data forthe pixel block is determined, and the presence of the reference data issearched in the pixel block regions. Tag information associated with thereference data is compared with (1) the span information, and/or (2) thebase address of the pixel blocks regions and one or more pixel blockregions likely to include the reference pixel blocks associated with thereference data are identified. Consider, for example, a reference pixelblock 204 associated with reference data and assigned to the third pixelblock region 202 c. The reference pixel block 204 is disposed in aregion common to each of the first pixel block region 202 a, the secondpixel block region 202 b, and the third pixel block region 202 c. Uponperforming a search for the reference pixel block 204 in the pixel blockregions, it is determined that the first pixel block region 202 a, thesecond pixel block region 202 b, and the third pixel block region 202 care likely to include the reference pixel block 204. Tag informationassociated with the reference data to be fetched is compared with thetag of reference pixel blocks in each of the three pixel block regions,and it is determined that the reference pixel block 204 is available inthe pixel block region 202 c.

If the reference pixel blocks are determined to be unavailable in thepixel block regions defined in the first cache 106 a, then it isdetermined whether the reference pixel blocks are available in thesecond cache 106 b. If it is determined that the reference pixel blocksare present in the second cache 106 b, then the reference pixel blocksare fetched from the second cache 106 b and cached in pixel blockregions for processing the plurality of pixel blocks corresponding tothe frame. If the reference pixel blocks are determined to beunavailable in the second cache 106 b, then the reference pixel blocksare fetched from the memory 104. In an embodiment, the caching operationis configured to be completed in about 100 cycles, and therefore aplurality of pixel blocks are processed simultaneously in order toachieve optimal performance. In an example embodiment, a set of fouradjacent pixel blocks are processed simultaneously. The four pixelblocks are simultaneously processed in order to exploit an overlapbetween reference data fetches for the four pixel blocks. This isexplained further herein with reference to FIGS. 3A-3C.

FIGS. 3A-3C illustrate an exemplary exploitation of an overlap between aplurality of reference data fetches, such as by using the system 100,according to an embodiment. As explained herein with reference to FIG.1, a multimedia frame is divided into macroblocks, such as, for example,16×16 pixel blocks, and each macroblock is further partitioned intoparts. FIG. 3A illustrates a macroblock 302 associated with themultimedia frame. The macroblock 302 is further partitioned into fouradjacent block partitions, such as a first block partition 304 a, asecond block partition 304 b, a third block partition 304 c, and afourth block partition 304 d. Each block partition includes a pluralityof pixel blocks (not shown in FIG. 3A). In an embodiment, each blockpartition includes four 4×4 pixel blocks. As explained herein withreference to FIG. 2, the pixel blocks associated with each of theplurality of block partitions are simultaneously processed in order toexploit an overlap between reference data fetches for the referencepixel blocks. Accordingly, for processing a plurality of pixel blocks ineach block partition, a reference region is determined. Thedetermination of the reference region is explained herein with referenceto FIG. 3B.

In order to process the plurality of pixel blocks in each blockpartition, reference regions (in the reference data) to be fetched aredetermined. In FIG. 3B, based on the locality of the pixel blockscorresponding to each block partition in a reference frame 306, fourreference regions (depicted by dotted squares in FIG. 3B), such as afirst reference region 308 a, a second reference region 308 b, a thirdreference region 308 c and a fourth reference region 308 d, aredetermined as corresponding to the plurality of pixel blocks in the fourpartitions. As explained herein with reference to FIG. 1, since the dataorganization in the memory 104 (or a pre-fetch buffer associated withthe memory 104) is depicted to be block-based, a minimum granularity offetching the reference pixels is block-based. Accordingly, it isdetermined that nine reference pixel blocks are to be fetched from thememory 104 corresponding to the first reference region 308 a in order tofetch reference data for pixel blocks associated with the first blockpartition. Further, it is determined that nine reference pixel blocks,six reference pixel blocks, and nine reference pixel blocks are to befetched from the memory 104 as corresponding to the second referenceregion 308 b, third reference region 308 c, and fourth reference region308 d, respectively. If the reference pixel blocks fetched for theadjacent reference regions overlap, then the reference pixel blocksfetched for one of the reference regions and cached in a pixel blockregion may be made available for subsequent fetches, and the availablereference pixel blocks are reused as explained herein with reference toFIG. 3C.

FIG. 3C illustrates a plurality of reference pixel block fetches for thefour adjacent block partitions of the pixel block 302. During theprocessing of the pixel blocks associated with the first block partition302 a, the pixel block regions defined in the first cache 106 a aredevoid of reference data. Accordingly, a presence of the nine referencepixel blocks that are to be implemented to process the pixel blocksassociated with the first block partition 304 a in the pixel blockregions of the first cache 106 a is determined. Initially, the pixelblock regions defined in the first cache 106 a are devoid of referencedata, and it is determined that the nine reference pixel blocks areunavailable in the first cache 106 a; moreover, the absence of each ofthe nine reference pixel blocks is recorded as a ‘MISS’ in the firstreference region 308 a. Since the desired reference data is determinedto be unavailable in the first cache 106 a, the nine reference pixelblocks are to be fetched from the memory 104. A set of four processingcycles (represented by circles in FIG. 3C) would be implemented to fetchthe desired nine reference pixel blocks. In an embodiment, four pixelblocks are fetched in each processing cycle, and, accordingly, a numberof additional pixel blocks in addition to the nine reference pixelblocks are fetched. Such pixel blocks are marked as “Not Relevant” (or“N/R”) in FIG. 3C. The nine reference pixel blocks are fetched from thememory 104 and cached in one or more pixel block regions in the firstcache 106 a.

As illustrated in FIG. 3B, a right edge 310 a of the first referenceregion 308 a and a left edge 310 b of the second reference region 308 blie in three common square blocks, which creates an overlap between thefirst reference region 308 a and the second region 308 b. As a result ofthe reference data fetch for the processing of the first block partition304 a, reference pixel blocks that are to be implemented to process thepixel blocks corresponding to the second block partition 304 b arealready fetched and cached in the first cache 106 a. As a result, uponchecking a presence of the nine reference pixel blocks that are to beimplemented to process the second block partition 304 b, it isdetermined that three reference pixel blocks are available, and,accordingly, the presence of three reference pixel blocks is recorded asa “HIT” and the absence of the remaining six reference pixel blocks isrecorded as a “MISS”. In order to fetch the six reference pixel blocks,four processing cycles are implemented. Some additional reference pixelblocks in addition to the six reference pixel blocks may be fetchedduring the fetching of the implemented reference data, and such pixelblocks are marked as “N/R”. The six reference pixel blocks are fetchedfrom the memory 104 and cached in one or more pixel block regions in thefirst cache 106 a.

Further, a lower edge 310 c of the first reference region 308 a and anupper edge 310 d of the third reference region 308 c lie in two commonsquare blocks creating an overlap between the first reference region 308a and the third reference region 308 c. As a result of the referencedata fetch for processing the first block partition 304 a, two referencepixel blocks that are to be implemented to process the pixel blockscorresponding to the third block partition 304 c are already fetched andcached in the first cache 106 a. On checking a presence of the sixreference pixel blocks that are to be implemented to process the thirdblock partition 304 c, it is determined that two reference pixel blocksare available and accordingly the presence of two reference pixel blocksis recorded as “HIT” and the absence of the remaining four referencepixel blocks is recorded as “MISS”. For fetching the four referencepixel blocks, two processing cycles are implemented. Some additionalreference pixel blocks in addition to the four reference pixel blocksmay be fetched during the fetching of the implemented reference data andsuch reference pixel blocks are marked as “N/R”. The four referencepixel blocks are fetched from the memory 104 and cached in one or morepixel block regions in the first cache 106 a.

Similarly, for processing the pixel blocks corresponding to the fourthpartition 304 d, an availability of the nine reference pixel blocks inthe pixel block regions of the first cache 106 a is checked andaccordingly, the reference pixel blocks are associated with a HIT or aMISS. Those pixel blocks, which are recorded as a MISS are fetched fromthe memory 104 and cached in the pixel block regions of the first cache106 a. The fetched reference data is utilized for processing the pixelblocks in the plurality of block partitions of the frame. The variousstages included in processing the multimedia data is explained hereinwith reference to FIG. 4A.

FIG. 4A depicts a simplified overview of an exemplary process flowillustrating a processing of a multimedia frame associated withmultimedia data in the system 100, according to an embodiment. In anembodiment, the processing of the multimedia frame is performed in threestages, such as a caching stage 402, a direct memory access (DMA) stage404, and a filtering stage 406. In the caching stage 402, at step 408,reference data that is to be implemented to process the frame isdetermined (for example, by the processing unit 102 of FIG. 1) andsubsequently a presence of the reference data is checked in the firstcache 106 a (for example, by the processing unit 102) at step 410.Though in FIG. 4A, a frame is depicted as an input to the caching stage402, in some embodiments, the frame is divided into blocks and furthereach block is partitioned and the reference data determined and fetchedfor the plurality of pixel blocks within each block partition of theframe (as explained herein with reference to FIGS. 3A-3C). In anembodiment, a size of reference pixel block to be fetched is determinedto be slightly bigger than the size of the corresponding pixel block ofthe frame. For example, for a 4×4 pixel block of the frame, a 9×9reference pixel block (five additional pixels on each side i.e., threeadditional pixels on left and two on right) is determined to be fetchedfrom a reference frame for interpolation during motion compensation.Similarly, for an 8×8 pixel block of the frame, a 13×13 reference pixelblock may be determined to be fetched from the reference frame forinterpolation.

As explained herein with reference to FIGS. 1 and 2, the processing unit102 may be configured to define pixel block regions in the first cache106 a. The pixel block regions are configured to be capable of cachingplurality of reference pixel blocks corresponding to the reference datapreviously fetched from one of the second cache 106 b and the memory104. On determining the reference data for the frame, one or more pixelblock regions that are likely to include the reference data areidentified (for example, using the processing unit 102 of FIG. 1). Apresence of one or more reference pixel blocks associated with thereference data in the identified pixel block regions is determined (forexample, using the processing unit 102 of FIG. 1).

In the DMA stage 404, at step 412, upon determining unavailability ofthe one or more of reference pixel blocks associated with the referencedata in the identified pixel block regions, one or more memory fetchcommands are generated (for example, by the processing unit 102 ofFIG. 1) to fetch the one or more reference pixel blocks from one of thesecond cache 106 b and the memory 104. In an embodiment, upondetermining an unavailability of the reference pixel blocks in the pixelblock regions, an availability of the reference pixel blocks is checkedin the second cache 106 b. If the reference pixel blocks are determinedto be available in the second cache 106 b, then the reference pixelblocks are fetched and cached in the pixel block regions of the firstcache 106 a for processing pixel blocks of the frame. If the referencepixel blocks are determined to be unavailable in the second cache 106 b,then the reference pixel blocks have to fetched from the memory 104. Atstep 414, reference data is fetched (for example, by the processing unit102 of FIG. 1) from the memory 104 based on the generated memory fetchcommand. At step 416, each of the one or more reference pixel blocksfetched from the memory 104/the second cache 106 b is assigned (forexample, by the processing unit 102 of FIG. 1) to a pixel block regionfrom among the one or more pixel block regions defined in the firstcache 106 a based on a predetermined criterion. In an embodiment, thepredetermined criterion includes, but is not limited to a locality ofthe reference pixel block within the reference frame and the locality ofthe pixel block region within the space defined by the reference frame.Subsequent to assignment, each of the one or more reference pixel blocksis associated (for example, by the processing unit 102 of FIG. 1) with atag based on the pixel block region so as to facilitate a search of thereference data in order to process subsequent pixel blocks of the frame.

In the filtering stage 406, at step 418, the one or more reference pixelblocks (corresponding to pixel blocks of the frame) fetched and assignedto a pixel block region from among the one or more pixel block regions,are read (for example, by the processing unit 102) and subjected toprocessing to obtain a predicted frame. The predicted frame maythereafter be used for processing (for example, encoding/decoding basedon motion compensation) of the frame of the multimedia data.

FIG. 4B illustrates an exemplary scheduling of read/write operationsassociated with the first cache 106 a during a processing of themultimedia frame, according to an embodiment. In an embodiment, thefirst cache 106 a is divided into multiple cache banks for scheduling ofthe read/write operations. In an embodiment, the first cache 106 a isdesigned to operate with three cache banks, for example, a cache bank 0,a cache bank 1, and a cache bank 2 in a pipeline/sequential manner. InFIG. 4B, the cache bank 0, the cache bank 1, and the cache bank 2 arerepresented by digits 0, 1, and 2, respectively. The pipeline approachprecludes the possibility of performing read and write operationssimultaneously into a given cache bank.

In an embodiment, the pipeline has three pipeline slots corresponding tovarious stages involved during processing of the multimedia data in thesystem 100. The three pipeline slots depicted in FIG. 4B are a frontslot 432, a DMA slot 434 and a back slot 436. In an embodiment, thefront slot 432 corresponds to processing stage including determinationof the reference data to be fetched from the memory 104 of FIG. 1 andthe generation of the memory fetch commands for fetching the referencedata, the DMA slot 434 corresponds to processing stage including thefetching of the reference data and assigning the fetched reference datato pixel block regions in the first cache 106 a (write operation on thefirst cache 106 a of FIG. 1), and the back slot 436 corresponds toprocessing stage including reading of the reference data (for example,by the processing unit 102 of FIG. 1) for configuring the predictionframe for processing of the frame associated with the multimedia data.The cache banks (0, 1 and 2) are subjected to the pipeline slots (432,434, and 436) in a sequential, recurring manner, through a plurality ofpasses 420-428 (represented by dotted vertical columns) of pipelineslots 432-436.

In FIG. 4B, in a first pass 420 of the pipeline slots (432-436), thecache bank 0 is subjected to the front slot 432. The reference data(corresponding to plurality of pixel blocks associated with the frame)to be fetched is determined. More specifically, the reference data thatis to be implemented to process the plurality of pixel blocks isidentified and the presence of the reference data in the first cache 106a and subsequently in the second cache 106 b is checked. On determiningunavailability of the reference data in the first cache 106 a and thesecond cache 106 b, the reference data is to be fetched from the memory104. The reference pixel blocks corresponding to the reference data tobe fetched from the memory 104 (for example, the reference pixel blocksrecorded as MISS in FIG. 3C) is assigned to the cache bank 0.

In an embodiment, an availability of space within a cache bank (e.g.,cache bank 0, cache bank 1 or cache bank 2) for accommodating thereference pixel blocks to be fetched is checked prior to performing thefetching operation. If sufficient space to accommodate the referencepixel blocks is available in the cache bank, then the reference pixelblocks are allotted to the cache bank and processed along with a groupof reference pixel blocks already present in the cache bank. However, ifthe space is determined to be insufficient, then reference pixel blocksare allotted to a new cache bank in a next subsequent pass. In anembodiment, a maximum possible number of reference pixel blocks areaccommodated in a cache bank. In an embodiment, reference pixel blockscorresponding to four macroblocks of the frame are allotted to a cachebank. In an embodiment, all reference pixel blocks corresponding to amacroblock of the frame may be included in a single cache bank. In anembodiment, if all reference pixel blocks corresponding to a macroblockcannot be accommodated in one cache bank, then the reference pixelblocks corresponding to that macroblock are included in the next cachebank during the next pass of the pipeline slots (432-436).

As depicted in FIG. 4B, during the first pass 420, the cache bank 0 issubjected to the front slot 432. During a second pass 422, the cachebank 1 is subjected to the front slot 432 and the cache bank 0 issubjected to DMA slot 434. All the pixel block regions defined duringthe front slot 432 are associated or tagged with the cache bank addressof the cache bank. In an embodiment, pixel block regions defined forcaching reference pixel blocks corresponding to the pixel blocks of thefirst block partition of the frame are associated with the cache bank 0.All pixel block regions defined for a subsequent block partition of theframe may be associated with the cache bank 1.

During a third pass 424, the cache bank 2 is subjected to front slot432, the cache bank 1 is subjected to DMA slot 434, and the cache bank 0is subjected to back slot 436 (filtering stage). Prior to subjecting thecache bank 2 to the DMA slot 434 in a fourth pass 426, all pixel blockregions in the cache bank 0 are invalidated and deleted as the pixelblock regions associated with the cache bank 0 would not be implementedand pixel block regions with the cache bank 1 would be retained forprocessing the cache bank 2. In an exemplary embodiment, the cache bank2 may include multimedia data associated with a reference pixel blockassociated with a row of pixel blocks within a reference frame. Thecache bank 1 may include multimedia data associated one or morereference pixel blocks to the left of the reference pixel block in therow of the reference pixel blocks and the cache bank 0 may includemultimedia data associated with one or more reference pixel blocks in atop row located above the row of the reference pixel block in thereference frame. The multimedia data associated with the one or morereference pixel blocks of cache bank 1 may be utilized while processingthe reference pixel block of cache bank 2, however, the multimedia dataassociated with the one or more reference pixel blocks of the cache bank0 may not be utilized while processing the reference pixel block ofcache bank 2 owing to the one or more reference pixel blocks of thecache bank 0 belonging to the top row. Therefore, one or more pixelblock regions of cache bank 0 may be invalidated and/or deleted whileprocessing cache bank 2 to make available space to accommodate otheradditional reference data that may be utilized during the processing ofthe multimedia data. In an embodiment, during a fifth pass 428, thecache bank 2 is subjected to the back slot 436. In an embodiment, aplurality of cache banks is simultaneously subjected to the front slot432, the DMA slot 434, and/or the back slot 436.

FIG. 5 illustrates an exemplary process of searching reference data inorder to process a plurality of pixel blocks associated with amultimedia frame, according to an embodiment. As explained herein withreference to FIGS. 3A-3C, for processing pixel blocks associated with ablock partition of the multimedia frame, reference regions for eachblock partition are determined and then their presence is checked, i.e.,searched in the first cache 106 a of FIG. 1. More specifically, apresence of the reference pixel blocks corresponding to each referenceregion is checked in one or more pixel block regions in the first cache106 a. Accordingly, a range check 502 of the reference pixel blocks isperformed, wherein a reference number (ref #) 504 and a locationco-ordinates (X, Y) 506 associated with the reference pixel blocks arecompared with a reference index 508 and span information/base address510 in the tag information associated with each pixel block region,respectively, to identify the pixel block regions likely to include thereference pixel blocks. As explained herein with reference to FIGS.3A-3C, the reference regions are determined within the reference framestored in the memory 104 and accordingly, the reference pixel blockswithin the reference region are tagged with the reference number (ref #)504 corresponding to the reference frame and location co-ordinates 506corresponding to the locality within the reference frame. A firstcomparison block 512 (depicted as CMP1 in FIG. 5) is utilized to performa comparison between the reference number (ref #) 504 and the referenceindex 508 of one or more pixel block regions. Further, a secondcomparison block 514 (depicted as CMP2 in FIG. 5) is utilized to performa comparison between location co-ordinates 506 and the spaninformation/base address 510.

In an embodiment, the span information is indicative of dimensions alonga length direction (for example, a height of the pixel block region) anda width direction (for example, a width of the pixel block region) ofeach pixel block region. During the comparison, it is determined if

X>=BA−X and <BA−(X+width of the pixel block region) and

Y>=BA−Y and <BA−(Y+height of the pixel block region)

wherein, BA is a base address of each of the one or more pixel blockregions.

Based on the output of the two comparison blocks 512 and 514, the pixelblock regions likely to include the reference pixel blocks aredetermined at block 516. Subsequently, an offset check 518 is performedto determine the presence of the reference pixel blocks within the pixelblock regions identified as likely to include the reference pixelblocks. At the offset check 518, it is determined that the offsetinformation included in location co-ordinates 506 (X, Y) of thereference pixel blocks matches with the offset of elements (referencepixel blocks previously fetched and cached in the pixel block regions)included in these pixel block regions. In FIG. 5, each pixel blockregion is depicted to include nine elements, however, it is noted thatthe pixel block regions may include more of fewer number of elements. Athird comparator block 520 is utilized for comparing tag information ofthe elements 522 a-522 i within each of the pixel block regions likelyto include the reference pixel blocks with the offset information of thereference pixel blocks. The third comparator block 520 (depicted as CMP3in FIG. 5) is depicted to include a number of comparators (each depictedas CMP within CMP3 520 in FIG. 5) equivalent of maximum number ofelements in a pixel block region for performing the comparisons in aparallel manner. For the one or more elements lying at the determinedpossible offset a plurality of availability tags associated with theelements at the determined possible offset is checked. In an embodiment,the reference pixel block is allowed to be present in a single pixelblock region in accordance with a design of the system 100 of FIG. 1. Inan embodiment, if the reference pixel block is present, an availabilitytag of the plurality of availability tags associated with the elementsis marked as a HIT 524 and if absent the availability tag is marked as aMISS. If the availability tag indicates presence of the reference pixelblock (e.g., HIT 524) an address of the element (e.g., HIT address 526)is encoded through an address encoder 528.

If the availability tag indicates absence of the reference block, a bankcheck is performed at a fourth comparator block 530 (depicted as CMP4 inFIG. 5) by comparing a current cache bank identification tag 532 (BANK#) with each of a plurality of cache bank identification tags 534associated with the identified pixel block regions (as explained hereinwith reference to FIG. 4B) to determine one or more pixel block regionswith the current cache bank identification tag 532. Subsequently, it ischecked if the determined pixel block regions with the current cachebank identification tag 534 have an availability of space to allot thereference pixel blocks absent in the identified pixel block regions. Anabsence of elements at the determined possible offset within thedetermined pixel block regions may indicate an availability of space.Also the absence of elements at the determined possible offset isindicated by a validity of a next pointer 536. The next pointer 536 iscompared with an output of the cache bank check at a fifth comparatorblock 538 (depicted as CMP5 in FIG. 5). If the cache bank check yieldsthe output and the next pointer 538 is valid, the address of the absentelement (e.g., MISS address 540) is determined using an encoder 542. Thereference pixel blocks are fetched (e.g., using the processing unit 102of FIG. 1) from the memory 104 or the second cache 106 b and assigned(e.g., using the processing unit 102 of FIG. 1) to one of the identifiedpixel block regions. If none of the identified pixel block regions withthe current cache bank identification tag 532 have availability ofspace, then a new pixel block region is created to assign the referencepixel blocks fetched from the memory 104 or the second cache 106 b.

In an embodiment, an availability of a space within the cache bank isdetermined for accommodating the reference pixel blocks to be fetchedfrom the memory. On determining availability of the space, the referencepixel blocks are allotted to the cache bank. In an embodiment, to reducea latency of data fetch from memory 104, the reference pixel blockscorresponding to the first reference region are fetched in combinationwith one or more additional reference pixel blocks aligned to be fetchedfrom the memory 104 using a single memory fetch command. In anembodiment, one or more additional reference pixel blocks to be fetchedalong with the reference pixel blocks are determined (e.g., using theprocessing unit 102 of FIG. 1) such that the reference pixel blocks andthe one or more additional reference pixel blocks are adjacent to oneanother within the reference frame. Also, the one or more additionalreference pixel blocks are determined such that the one or moreadditional reference pixel blocks and the reference pixel blockstogether form a rectangular region (contiguous region) within thereference frame. In an embodiment, the one or more additional referencepixel blocks and the reference pixel blocks correspond to a blockpartition from among a plurality of block partitions within the frame.In an embodiment, the reference pixel blocks and the one or moreadditional reference pixel blocks may belong to adjacent blockpartitions within the reference frame and may together form arectangular region (contiguous region) within the reference frame. Theone or more additional reference pixel blocks and the reference pixelblock may be fetched together from the memory 104 based on a singlememory fetch command.

In an embodiment, the reference pixel block and the one or moreadditional reference pixel blocks of a block partition may be mergedtogether with one or more reference pixel blocks of an adjacent blockpartition, while being aligned to be fetched. The reference pixel block,the one or more additional reference pixel blocks, and the one or morereference pixel blocks may form a rectangular (contiguous region) andmay be fetched from the memory 104 based on a single memory fetchcommand. The one or more additional reference pixel blocks and thereference pixel blocks may be allotted to same or different cache bankswhile being aligned to be fetched from the memory 104. In an embodiment,a memory fetch command may be created (e.g., using the processing unit102 of FIG. 1) for the cache bank for fetching the allotted referencepixel block and the one or more additional reference pixel blocks fromthe memory 104. The allotted reference pixel block and the one or moreadditional reference pixel blocks may be fetched (e.g., using theprocessing unit 102 of FIG. 1) from the memory 104 based on the createdmemory fetch command. Since the reference pixel block and the one ormore additional reference pixel blocks are fetched together from thememory, a total number of tags used for fetching the reference data fromthe memory may be reduced facilitating a conformance with the systemperformance specifications.

In an embodiment, the first cache 106 a may not involve predictivepre-fetch due to the organization of the cache unit 106 and the system100 and each of the reference pixel blocks unavailable in the firstcache 106 a are to be fetched separately from the memory 104. Each ofthe reference pixel blocks may be assigned a tag. In some platforms(e.g., OMAP™), a number of tags allowable is limited and assigning eachof the reference pixel blocks the tag, renders it difficult to meet asystem performance specification. Additionally, a size of the referencedata fetch is maintained within a maximum burst size allowable in thesystem 100. In an embodiment, a break down logic is implemented tomaintain the size of the reference data fetch within the maximum burstsize. The maximum burst size includes, for example eight data phases.The reference data fetching from the memory 104 is explained further inFIGS. 6A-6C.

FIGS. 6A-6C illustrate exemplary fetching reference pixel blocksadjacent to one another within a reference frame associated withmultimedia data in system 100 of FIG. 1 according to an embodiment. FIG.6A depicts two adjacent block partitions 602 a and 602 b associated withthe reference frame. Each of the two adjacent block partitions 602 a and602 b include 16 reference pixel blocks as illustrated in FIG. 6A. Onperforming a search for reference data for processing one or more pixelblocks corresponding to the block partitions 602 a and 602 b, it isdetermined that the shaded group of reference pixel blocks 604 a, 604 b,604 c and 604 d are the reference pixel blocks unavailable in a cacheunit 106 and are to be fetched from a memory 104 of FIG. 1.

Each of the shaded group of reference pixel blocks 604 a, 604 b, and 604c include four reference pixel blocks and the shaded group of referencepixel block 604 d includes a pair of reference pixel blocks asillustrated in FIG. 6A. Instead of generating a reference pixel blockfetch command for each reference pixel block in each shaded group ofreference pixel blocks 604 a, 604 b, 604 c and 604 d (resulting ingenerating four reference pixel block fetch commands each for processingshaded group of reference pixel blocks 604 a, 604 b and 604 c, and tworeference pixel block fetch commands for processing shaded group ofreference pixel blocks 604 d), the reference pixel block fetch commandsmay be combined As explained herein with reference to FIGS. 6B and 6C.

In FIG. 6B, reference pixel block fetches for adjacent pixel blocks in ablock partition are combined, thereby optimizing the system capacity andimproving performance. For example, one reference pixel block fetchcommand may be generated for each of the shaded group of reference pixelblocks 604 a, 604 b, 604 c and 604 d. The reference pixel block fetchcommands are generated by combining reference pixel block fetch commandsfor individual reference pixel blocks in shaded groups of referencepixel blocks 604 a, 604 b, 604 c and 604 d as depicted in FIG. 6B. Forexample, a reference pixel block fetch command 606 a may be utilized forfetching the shaded group of reference pixel blocks 604 a. Similarly,reference pixel block fetch commands 606 b, 606 c and 606 d may beutilized for fetching the shaded group of reference pixel blocks 604 b,604 c and 604 d. A number of reference pixel blocks fetches are therebyreduced from 14 to 4, thereby increasing caching performance.

In FIG. 6C, reference pixel block fetches for adjacent pixel blocks inadjacent block partition (such as block partitions 602 a and 602 b) arecombined. In addition to generating the reference pixel block fetchcommands 606 a and 606 d, the reference data fetch for adjacent shadedgroup of reference pixel blocks 604 b and 604 c (in adjacent blockpartitions 602 a and 602 b) are combined into single reference pixelblock fetch command 606 e for fetching the shaded group of referencepixel blocks 604 b and 604 c. A number of reference pixel blocks fetchesare thereby reduced from 14 to 3, thereby further increasing cachingperformance.

FIG. 7 is a flow chart illustrating an exemplary method 700 formultimedia data processing, according to an embodiment. In anembodiment, the method 700 may be implemented by a system, such as thesystem 100 of FIG. 1. Operations of the flowchart, and combinations ofoperation in the flowchart, may be implemented by various means, such ashardware, firmware, processor, circuitry and/or other device associatedwith execution of software including one or more computer programinstructions. The operations of the method 700 are described with helpof the system 100. However, the operations of the method can bedescribed and/or practiced by using any other system. The method 700starts at operation 702. At operation 702, one or more pixel blockregions, such as the pixel blocks regions explained herein withreference to FIG. 2, are defined in a first cache (for example, firstcache 106 a of FIG. 1) in order to cache a plurality of reference pixelblocks corresponding to reference data. In an embodiment, the referencedata may be fetched from one of a memory (for example, memory 104 ofFIG. 1) and a second cache (for example, second cache 106 b of FIG. 1).In an embodiment, the reference data may correspond to a reference frameof the one or more reference frames stored in the memory.

As explained herein with reference to FIG. 1, each pixel block regionmay be considered as an allotment of storage space within the firstcache, which is capable of caching one or more reference pixel blocks.One or more such storage spaces may be defined (for example, by usingprocessing unit such as the processing unit 102 of FIG. 1) within thefirst cache in order to cache the plurality of reference pixel blocksfetched from the memory. In an embodiment, number of pixel block regionsto be defined may be determined based on a video compression paradigm.Examples of the video compression paradigms include, but are not limitedto video coding experts group (VCEG), H.120, H.261, moving picturesexperts group (MPEG), MPEG-1 Part 2, H.262 or MPEG-2 Part 2, H.263,MPEG-4 Part 2, H.264 or MPEG-4 AVC, VC-2 (Dirac), high efficiency videocoding (HEVC) and the like.

In an embodiment, each pixel block region is defined through spaninformation, a base address, a cache bank identification tag, and/or areference index. The span information is indicative of dimensions alonga length direction (e.g., a height) and a width direction (e.g., awidth) of each pixel block region. The base address is offset of a topleft address of each pixel block region from an origin pre-determinedwithin a space defined by the reference frame and is indicative of thelocality of the pixel block region within the space defined by thereference frame. The base address of each pixel block region isexpressed in terms of x and y coordinates. The cache bank identificationtag is indicative of a cache bank each pixel block region is associatedwith. The reference index is indicative of the reference frameassociated with each pixel block region. For example, if the referencedata in the memory 104 comprises 32 reference frames and the pixel blockregion is associated with reference frame #5 of the 32 reference frames,then the reference index of the pixel block region may indicate thereference frame from which the reference pixel blocks included in thepixel block region are fetched.

At operation 704, a reference pixel block from among the plurality ofreference pixel blocks is assigned to a pixel block region from amongthe one or more pixel block regions based on a predetermined criterion.The predetermined criterion includes, but is not limited to a localityof the reference pixel block within the reference frame and a localityof the pixel block region within the space defined by the referenceframe. In an embodiment, reference pixel blocks belonging to a singlereference frame is assigned to a pixel block region from among the oneor more pixel block regions. In an embodiment, a pixel block region issparsely filled and includes a few reference pixel block entries (alsoreferred to as elements). In an embodiment, a pixel block region fromamong the one or more pixel block regions includes nine elements. In anembodiment, each element of the one or more elements associated with apixel block region is assigned a specific location within the pixelblock region based on a locality of each element within the spacedefined by the corresponding reference frame. In an embodiment, a cachebank identification tag (as explained previously) is associated witheach pixel block region to indicate the cache bank each of the one ormore pixel block regions is defined within. At operation 706, thereference pixel block is associated with a tag based on the pixel blockregion so as to facilitate a search of the reference data in order toprocess a plurality of pixel blocks associated with a multimedia frame.The searching of the reference data for processing of the multimediaframe is explained in FIGS. 8A-8B.

FIGS. 8A-8B collectively show a flow chart illustrating an exemplarymethod 800 of searching reference data in order to perform processing ofthe multimedia frame, according to an embodiment. In an embodiment, thesystem 800 may be implemented by a system, such as the system 100 ofFIG. 1. Operations of the flowchart, and combinations of operation inthe flowchart, may be implemented by various means, such as hardware,firmware, processor, circuitry and/or other device associated withexecution of software including one or more computer programinstructions. The operations of the method 800 are described with helpof the system 100. However, the operations of the method can bedescribed and/or practiced by using any other system. The method 800starts at operation 802. At operation 802, a first reference regioncorresponding to a plurality of pixel blocks in a block partition fromamong a plurality of block partitions in the multimedia frame isdetermined for processing the multimedia frame. For example, for a 4×4pixel block of the multimedia frame, a 9×9 reference region (fiveadditional pixels on each side i.e., three additional pixels on left andtwo on right) is determined to be fetched from a reference frame forinterpolation during motion compensation. Similarly, for an 8×8 pixelblock of the frame, a 13×13 reference region block may be determined tobe fetched from the reference frame. As explained herein with referenceto FIGS. 3A-3C, the first reference region is determined within thereference frame stored in a memory (for example, memory 104 of FIG. 1)and accordingly, the reference pixel blocks within the first referenceregion are tagged with a reference number corresponding to the referenceframe and location co-ordinates corresponding to the locality with thereference frame. At operation 804, pixel block regions from among theone or more pixel block regions of a first cache (for example, firstcache 106 a of FIG. 1) likely to include the first reference region areidentified by comparing tag information associated with the firstreference region with span information associated with each pixel blockregion. The tag information associated with the first reference regionincludes a reference number (for example, ref #504 of FIG. 5) andlocation co-ordinates (for example, (X, Y) 506 of FIG. 5). The spaninformation is indicative of dimensions along a length direction (e.g.,a height) and a width direction (e.g., a width) of each pixel blockregion. During the comparison, it is determined if

X>=BA−X and <BA−(X+width of the pixel block region) and

Y>=BA−Y and <BA−(Y+height of the pixel block region)

wherein, BA is a base address of each of the one or more pixel blockregions and (X, Y) is location coordinates associated with the firstreference region.

For the identified pixel block regions an offset check is performed todetermine the presence of the reference pixel blocks within theidentified pixel block regions. During the offset check a possibleoffset of the first reference region within each of the identified pixelblock regions is determined based on the span information associatedwith each of the identified pixel block regions and a location of thefirst reference region within the reference frame. A presence of thefirst reference region at the determined possible offset in each of theidentified pixel block regions is determined by checking a plurality ofavailability tags associated with each reference pixel block at thedetermined possible offset. At operation 806, a presence of the firstreference region at a determined possible offset in each of theidentified pixel block regions is determined by checking a plurality ofavailability tags associated with reference pixel blocks at thedetermined possible offset. In an embodiment, if the reference pixelblock is present, an availability tag associated with the referencepixel block is marked as a HIT and if the reference pixel block isabsent the availability tag is marked as a MISS. In an embodiment, themarking of the availability tags may be performed as explained hereinwith reference to FIG. 3C.

At operation 808, it is verified if the first reference region isdetermined to be present in the pixel block regions of the first cache.If the first reference region is not present in the pixel block regionsof the first cache a presence of the first reference region in a secondcache (for example, second cache 106 b) is determined at operation 810.On the contrary, on determining the presence of the first referenceregion in the pixel block regions of the first cache, operation 812 isperformed. At operation 812, the plurality of pixel blocks in the blockpartition in of the multimedia frame is processed based on the firstreference region. An example of processing of the multimedia frame mayinclude performing motion compensation for frames of the multimedia datafor encoding/decoding purposes. On determining a presence of the firstreference region in the second cache at operation 810, operation 814 issubsequently performed. At operation 814, it is verified if the firstreference region is determined to be present in the second cache. If thefirst reference region is determined to be present in the second cache,then operation 816 is performed. At operation 816, the reference pixelblocks associated with the first reference region is fetched from thesecond cache into the first cache.

Alternatively, if the first reference region is determined to be absentin the second cache, at operation 818, a memory fetch command isgenerated for fetching reference pixel blocks associated with the firstreference region from the memory. In an embodiment, the memory fetchcommand is generated (e.g., using processing unit 102 of FIG. 1) for acache bank of a plurality of cache banks associated with the firstcache. In an embodiment, one or more additional reference pixel blocksto be fetched along with the first reference region is determined, suchthat the one or more additional reference pixel blocks and one or morereference pixel blocks associated with the first reference region areadjacent to one another within the reference frame and form arectangular region (contiguous region) within the reference frame. In anembodiment, a memory fetch command is generated to fetch the firstreference region and the one or more additional reference pixel blocksas explained herein with reference to FIGS. 6A-6C. In an embodiment, theone or more additional reference pixel blocks and the first referenceregion correspond to a block partition from among a plurality of blockpartitions within the reference frame. In one embodiment, the one ormore additional reference pixel blocks and the first reference regioncorrespond to adjacent block partitions within the reference frame. Theone or more additional reference pixel blocks and the first referenceregion may be associated with same or different cache banks.

At operation 820, the reference pixel blocks associated with the firstreference region are fetched from the memory, based on the generatedmemory fetch command. In an embodiment, the first reference region isfetched along with the one or more additional reference pixel blocksfrom the memory based on the generated memory fetch command. A minimumgranularity for fetching each of the first reference region from thememory is matched with the size of the pre-fetch buffer associated withthe memory. The reference pixel blocks may be fetched from the memory asexplained herein with reference to FIGS. 6A-6C. Once the reference pixelblocks are fetched either from the memory or the second cache, thenoperation 822 is performed.

At operation 822, the fetched reference pixel blocks are assigned to oneor more pixel block regions in the first cache based on a predeterminedcriterion. The predetermined criterion includes, but is not limited to alocality of the reference pixel block within a space defined by thereference frame. A cache bank associated with the assigned referencepixel blocks is configured to expire upon all the reference pixel blocksassociated with the cache bank being read from the cache bank. Uponexpiration of the cache bank, the reference pixel blocks associated withthe cache bank are deleted from the first cache and are assigned to acache bank associated with the second cache for processing subsequentpixel blocks associated with the multimedia frame. In an embodiment, anavailability of a space within the second cache is determined in orderto cache the fetched one or more reference pixel blocks. On determiningavailability of the space, the fetched reference pixel blocks are cachedin the second cache. Alternatively, on determining an unavailability ofspace, one or more previously cached reference pixel blocks in thesecond cache are deleted and an origin of the second cache is shifted bya predetermined margin in order to cache the fetched reference pixelblocks. Each reference pixel block assigned to the first cache issubjected to operation 824. At operation 824, each reference pixel blockis associated with a tag based on the pixel block region so as tofacilitate a search of the first reference region during a processing ofthe multimedia frame.

Without in any way limiting the scope, interpretation, or application ofthe claims appearing below, advantages of one or more of the exemplaryembodiments disclosed herein include a reduction in a memory bandwidthconsumption and consequent reduction in power dissipation by the memoryand increase in a playback time (for example, the playback time may beincreased by three hours) associated with the multimedia data. Definingpixel block regions in a first cache and tagging reference pixel blocksas offset from the base address of the corresponding pixel block regionreduces a size of the tagging reference data, thereby reducing a cost ofcomparison and leading to a sizable savings in power consumption. Also,by using a second cache, a total number of processing cycles is reducedas the number of processing cycles (e.g., 10 processing cycles) utilizedfor fetching the reference data from the second cache is lesser than thenumber of processing cycles (e.g., 100 processing cycles) utilized forfetching the reference data from the memory. Also, by grouping referencepixel blocks associated with adjacent pixel blocks in the frame ofmultimedia data, a number of data phases per burst is increased to about8 as opposed to 1 in an alternative caching paradigm. The increased dataphases per burst leads to a reduction in interconnect and memoryinterface power.

Additionally, since a size of reference data fetch is matched with amaximum size of a pre-fetch buffer of the memory, power is usedefficiently in the system as an equal amount of power is dissipated forfetching one pixel block or one or more pixel blocks of size equivalentto the pre-fetch buffer. The system disclosed herein is configured tooperate in a pipeline manner to enable efficient memory fetch operations(e.g., DMA). The pipeline operation of three cache banks described inthe detailed description of FIG. 4B eliminates complex logic to maintaincoherency and allows parallel and efficient operation of various stages.Furthermore, in the present technology, a memory specification islowered owing to higher associativity. Moreover, the method and systemdisclosed herein enables achieving a frame rate close to 120 frames persecond.

Although the present technology has been described with reference tospecific exemplary embodiments, it is noted that various modificationsand changes may be made to these embodiments without departing from thebroad spirit and scope of the present technology. For example, thevarious devices, modules, analyzers, generators, etc., described hereinmay be enabled and operated using hardware circuitry (for example,complementary metal oxide semiconductor (CMOS) based logic circuitry),firmware, software and/or any combination of hardware, firmware, and/orsoftware (for example, embodied in a machine-readable medium). Forexample, the various electrical structures and methods may be embodiedusing transistors, logic gates, and electrical circuits (for example,application specific integrated circuit (ASIC) circuitry and/or inDigital Signal Processor (DSP) circuitry).

Particularly, the system 100, the processing unit 102, the memory 104and the cache unit 106 may be enabled using software and/or usingtransistors, logic gates, and electrical circuits (for example,integrated circuit circuitry such as ASIC circuitry). Variousembodiments of the present disclosure may include one or more computerprograms stored or otherwise embodied on a computer-readable medium,wherein the computer programs are configured to cause a processor orcomputer to perform one or more operations. A computer-readable mediumstoring, embodying, or encoded with a computer program, or similarlanguage, may be embodied as a tangible data storage device storing oneor more software programs that are configured to cause a processor orcomputer to perform one or more operations. Such operations may be, forexample, any of the steps or operations described herein. Additionally,a tangible data storage device may be embodied as one or more volatilememory devices, one or more non-volatile memory devices, and/or acombination of one or more volatile memory devices and non-volatilememory devices.

Also, techniques, devices, subsystems and methods described andillustrated in the various embodiments as discrete or separate may becombined or integrated with other systems, modules, techniques, ormethods without departing from the scope of the present technology.Other items shown or discussed as directly coupled or communicating witheach other may be coupled through some interface or device, such thatthe items may no longer be considered directly coupled with each otherbut may still be indirectly coupled and in communication, whetherelectrically, mechanically, or otherwise, with one another. Otherexamples of changes, substitutions, and alterations ascertainable by oneskilled in the art, upon or subsequent to studying the exemplaryembodiments disclosed herein, may be made without departing from thespirit and scope of the present technology. Additionally, for purposesof illustration, the detailed description refers to pixel blocksassociated with a frame; however the scope of the method and systemdisclosed herein is not limited to the pixel blocks but may be extendedto include coding units as per the HEVC paradigm.

It should be noted that reference throughout this specification tofeatures, advantages, or similar language does not imply that all of thefeatures and advantages should be or are in any single embodiment.Rather, language referring to the features and advantages may beunderstood to mean that a specific feature, advantage, or characteristicdescribed in connection with an embodiment may be included in at leastone embodiment of the present technology. Thus, discussions of thefeatures and advantages, and similar language, throughout thisspecification may, but do not necessarily, refer to the same embodiment.

Various embodiments of the present disclosure, as discussed above, maybe practiced with steps and/or operations in a different order, and/orwith hardware elements in configurations which are different than thosewhich are disclosed. Therefore, although the technology has beendescribed based upon these exemplary embodiments, it is noted thatcertain modifications, variations, and alternative constructions may beapparent and well within the spirit and scope of the technology.Although various exemplary embodiments of the present technology aredescribed herein in a language specific to structural features and/ormethodological acts, the subject matter defined in the appended claimsis not necessarily limited to the specific features or acts describedabove. Rather, the specific features and acts described above aredisclosed as exemplary forms of implementing the claims.

What is claimed is:
 1. A method, comprising: defining one or more pixelblock regions in a first cache so as to cache a plurality of referencepixel blocks corresponding to reference data; assigning a referencepixel block from among the plurality of reference pixel blocks to apixel block region from among the one or more pixel block regions basedon a predetermined criterion; and associating the reference pixel blockwith a tag based on the pixel block region so as to facilitate a searchof the reference data in order to process a plurality of pixel blocksassociated with a multimedia frame.
 2. The method of claim 1, whereinthe pixel block region is defined through at least one of spaninformation indicative of dimensions along a length direction and awidth direction of the pixel block region, a base address, a referenceindex indicative of a reference frame associated with the pixel blockregion, and a cache bank identification tag indicative of a cache bankassociated with the pixel block region.
 3. The method of claim 1,wherein the search comprises: determining a first reference regioncorresponding to the plurality of pixel blocks in a first blockpartition from among a plurality of block partitions in the multimediaframe; identifying one or more pixel block regions from among the one ormore pixel block regions that are likely to include the first referenceregion by comparing tag information associated with the first referenceregion with span information associated with the one or more pixel blockregions; and determining a presence of one or more reference pixelblocks associated with the first reference region in the identified oneor more pixel block regions.
 4. The method of claim 3, whereindetermining the presence of the one or more reference pixel blockscomprises: determining a possible offset of the first reference regionwithin the identified one or more pixel block regions based on the spaninformation and a location of the first reference region within areference frame associated with the reference data; and determining apresence of the first reference region at the determined possible offsetin the identified one or more pixel block regions by checking aplurality of availability tags associated with the one or more referencepixel blocks at the determined possible offset.
 5. The method of claim3, further comprising: determining a presence of the one or morereference pixel blocks in a second cache if the first reference regionis determined to be absent in the identified one or more pixel blockregions; and fetching the one or more reference pixel blocks associatedwith the first reference region from one of: the second cache if thefirst reference region is determined to be present in the second cache;and a memory if the first reference region is determined to be absent inthe second cache.
 6. The method of claim 5, further comprising: cachingthe fetched one or more reference pixel blocks in the first cache inorder to process the plurality of pixel blocks associated with themultimedia frame.
 7. The method of claim 6, further comprising: cachingthe fetched one or more reference pixel blocks in the second cache uponthe one or more reference pixel blocks being read from the first cachein order to process the subsequent pixel blocks associated with themultimedia frame
 8. The method of claim 7, wherein caching the fetchedone or more reference pixel blocks in the second cache comprises:determining an availability of a space within the second cache forcaching the fetched one or more reference pixel blocks; and performingone of: caching the fetched one or more reference pixel blocks in thesecond cache if the space is determined to be available within thesecond cache; and deleting one or more previously cached reference pixelblocks in the second cache if the space is determined to be unavailablewithin the second cache, wherein an origin of the second cache isshifted by a predetermined margin for caching the fetched one or morereference pixel blocks on deleting the one or more previously cachedreference pixel blocks.
 9. The method of claim 5, wherein a minimumgranularity for fetching a reference pixel block from among the one ormore reference pixel blocks associated with the first reference regionfrom the memory is matched with a minimum granularity of caching in apre-fetch buffer associated with the memory.
 10. The method of claim 9,wherein the fetching of the one or more reference pixel blocksassociated with the first reference region from the memory comprises:determining one or more additional reference pixel blocks to be fetchedalong with the one or more reference pixel blocks associated with thefirst reference region, wherein the one or more additional referencepixel blocks and the first reference region are adjacent to one anotherwithin the reference frame and together form a rectangular region withinthe reference frame.
 11. The method of claim 10, wherein the one or moreadditional reference pixel blocks and the first reference regioncorrespond to a block partition from among a plurality of blockpartitions within the reference frame.
 12. The method of claim 10,wherein the one or more additional reference pixel blocks and the firstreference region correspond to adjacent block partitions within thereference frame.
 13. The method of claim 10, wherein the fetching of theone or more reference pixel blocks associated with the first referenceregion from the memory further comprises: generating a memory fetchcommand so as to fetch the one or more additional reference pixel blocksand the one or more reference pixel blocks associated with the firstreference region from the memory; and fetching the one or moreadditional reference pixel blocks and the one or more reference pixelblocks associated with the first reference region from the memory basedon the generated memory fetch command.
 14. A system, comprising: amemory configured to store one or more reference frames corresponding toreference data; a cache unit communicatively associated with the memoryand comprising a first cache and a second cache; and a processing unitcommunicatively associated with the memory and the cache unit, theprocessing unit configured to: define one or more pixel block regions inthe first cache so as to cache a plurality of reference pixel blockscorresponding to the reference data; assign a reference pixel block fromamong the plurality of reference pixel blocks to a pixel block regionfrom among the one or more pixel block regions based on a predeterminedcriterion; and associate the reference pixel block with a tag based onthe pixel block region so as to facilitate a search of the referencedata in order to process a plurality of pixel blocks associated with amultimedia frame.
 15. The system of claim 14, wherein the processingunit is further configured to: determine a first reference regioncorresponding to the plurality of pixel blocks in a first blockpartition from among a plurality of block partitions in the multimediaframe; identify one or more pixel block regions from among the one ormore pixel block regions that are likely to include the first referenceregion by comparing tag information associated with the first referenceregion with span information associated with the one or more pixel blockregions; and determine a presence of one or more reference pixel blocksassociated with the first reference region in the identified one or morepixel block regions.
 16. The system of claim 15, wherein the processingunit is further configured to: determine a presence of the one or morereference pixel blocks in the second cache if the first reference regionis determined to be absent in the identified one or more pixel blockregions; and fetch the one or more reference pixel blocks associatedwith the first reference region from one of: the second cache if thefirst reference region is determined to be present in the second cache;and the memory if the first reference region is determined to be absentin the second cache.
 17. The system of claim 16, wherein the fetching ofthe one or more reference pixel blocks associated with the firstreference region from the memory comprises: determining one or moreadditional reference pixel blocks to be fetched along with the one ormore reference pixel blocks associated with the first reference region,wherein the determined one or more reference pixel blocks and the firstreference region correspond to one of a block partition and an adjacentblock partition from among a plurality of block partitions within thereference frame.
 18. A computer-readable medium storing a set ofinstructions that when executed cause a computer to perform a method,the method comprising: defining one or more pixel block regions in afirst cache so as to cache a plurality of reference pixel blockscorresponding to reference data; assigning a reference pixel block fromamong the plurality of reference pixel blocks to a pixel block regionfrom among the one or more pixel block regions based on a predeterminedcriterion; and associating the reference pixel block with a tag based onthe pixel block region so as to facilitate a search of the referencedata in order to process a plurality of pixel blocks associated with amultimedia frame.
 19. The computer-readable medium of claim 18, whereinthe search of the reference data comprises: determining a firstreference region corresponding to the plurality of pixel blocks in afirst block partition from among a plurality of block partitions in themultimedia frame; identifying one or more pixel block regions from amongthe one or more pixel block regions that are likely to include the firstreference region by comparing tag information associated with the firstreference region with span information associated with the one or morepixel block regions; and determining a presence of one or more referencepixel blocks associated with the first reference region in theidentified one or more pixel block regions.
 20. The computer-readablemedium of claim 19, further comprising: determining a presence of theone or more reference pixel blocks in a second cache if the firstreference region is determined to be absent in the identified one ormore pixel block regions; and fetching the one or more reference pixelblocks associated with the first reference region from one of: thesecond cache if the first reference region is determined to be presentin the second cache; and a memory if the first reference region isdetermined to be absent in the second cache.